Modeling nanoelectronic CNN cells: CMOS, SETs and QCAs

Abstract

Summary form only given, as follows. We investigate the use of nanoelectronic structures in cellular neural network (CNN) architectures, for future high-density and low-power CMOS-nanodevice hybrid circuits. We present simulation results for Single Electron Tunneling (SET) transistors configured as a voltage-to-current transducer for CNN cells. We also present an example of quantum-dot cellular arrays which may be used to realize binary CNN algorithms. Nanoelectronics offers the promise of ultra-low power and ultra-high integration density. Several device structures have been proposed and realized experimentally, yet the main challenge remains the organization of these devices in new circuit architectures. Here, we investigate the use of nanodevices in CNN architectures. Specifically, we focus on nanostructures based on SET devices and Coulomb-coupled quantum-dot arrays, the so-called Quantum-Dot Cellular Automata (QCA). CNN-type architectures for nanostructures are motivated by the following considerations: on the one hand, locally-interconnected architectures appear to be natural for nanodevices where some of the connectivity may be provided by direct physical device-device interactions. On the other hand, CNN arrays with sizes on the order of 1000-by-1000 (which are desirable for applications such as image processing) will require the use of nanostructures since such integration densities are beyond what can be achieved by scaling conventional CMOS devices.