Modeling Ion-Induced Pulses in Radiation-Hard SOI Integrated Circuits

Abstract

A common technique for hardening a circuit cell against single-event effects (SEE) is to use an RC delay or other time delay technique to slow down the response of a storage or memory cell. In order for this to work, we must have a good model for the duration of the output voltage pulse due to the ion strike on a given cell. Two-dimensional simulations determine the output voltage pulse shape due to an ion strike on a circuit cell within an integrated circuit. For SOI, the worst-case pulse occurs when the ion strike is near the center of the NMOS body (under the gate). It is very desirable to have a simple SPICE model for the SEE behavior because of the large number of circuit cells that need to be characterized. Two-dimensional (2D) simulations are translated into a ID format, from which closed-form physics-based equations are derived, which are then used in SPICE simulations. Test chips from a 0.15 mum SOI process are used to experimentally determine the LET threshold of six different circuits. The SPICE predictions of LET threshold are in good agreement with the experimental results. Because the SEE pulse widths in SOI circuits are much shorter than those in comparable bulk CMOS circuits, time-delay radiation hardening of SOI can be achieved with much less compromise of the speed of storage or memory cells.