Modeling hot-carrier effects in polysilicon emitter bipolar transistors

Abstract

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by Delta I/sub B/ varies as I/sub R//sup m+n/t/sup n/ where n approximately=0.5 and m approximately=0.5. The more complex relationships of Delta beta (I/sub C/, I/sub R/, t) and beta (I/sub C/, I/sub R/, t) result naturally from the simple Delta I/sub B/ model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology. >