Modeling for Spin-FET and Design of Spin-FET-Based Logic Gates

Abstract

Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model.