Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via

Abstract

A new approach to implement integrated capacitors with an excellent capacitance density, called the “3-D embedded capacitor,” is investigated. It is realized by embedding metal–insulator–metal (MIM) layers onto the trenches of through-silicon vias prior to copper filling. An ultrahigh capacitance density of 5621.8 nF/mm2 was envisioned according to our model, which is $\sim 13\times $ of 440.0 nF/mm2 from a conventional trench capacitor with the same design parameters. A set of prototypes was fabricated and characterized for assessment of structural integrity and electrical performance of the 3-D embedded capacitors. Scanning electron microscope, transmission electron microscope, and energy-dispersive X-ray spectroscopy analysis results show a good step coverage and stoichiometry of the MIM layers deposited. The capacitance density of up to 3856.4 nF/mm2 was achieved for the prototypes with MIM layers formed by atomic layer deposition. A leakage current density as low as $1.61 \times 10^{-7}$ A/cm2 at 4.3 V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3776.6 nF/mm2.