Abstract
In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9% as compared to the actual values.
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