Abstract
In this paper, we propose an analytical model that accurately accounts for all the load per independent unit that has to be driven by the clock distribution network, the power budget required by the clock generation circuitry and the energy required to distribute the clock all around the chip. Such a model is of extreme importance in completing a framework for architectural-level decisions on total power budget. The validation of the analytical model for the clock generation circuit energy using VLSI layouts shows an average error of 9% as compared to the actual values.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.