Modeling electromigration and the void nucleation in thin-film interconnects of integrated circuits

Abstract

The modern tendency for increasing the productivity of microelectronic devices at the expense of the size shrinkage and the development of densely packed multilevel microelectronic structures stipulates the rising concern for the reliability of integrated circuits. The damage of integrated circuits is mainly caused by electromigration in thin-film interconnects. The current-induced redistribution of vacancies and the action of vacancy sinks/sources lead to heterogeneous volume deformations, which, in turn, cause the rise of mechanical stresses. The interconnect failure is initiated by the nucleation of voids taking place on the crystalline structure heterogeneities like triple points, inclusions, etc. or in the plug region of multilevel metallizations. In the latter case the interconnect damage is also caused by the edge depletion. Mechanical stresses induced by electromigration strongly influence the nucleation process. In the present work we propose a general 3D model for electromigration and the rise of mechanical stresses in a passivated aluminum interconnect. A system of differential equations describing electromigration and induced deformation of an interconnect is derived. We also propose a kinetic model for the void nucleation, elaborated on the basis of the classical theory of the new phase nucleation. Integral equations for the time to the void nucleation are deduced. Based on these models numerical calculations for the void formation in a triple point of the interconnect crystalline structure and for both failure mechanisms in the plug region have been carried out. The times to nucleation and characteristic sizes of voids are calculated as functions of temperature and electric current density. The results obtained agree well with experimental data.