Modeling and test for parasitic resistance and capacitance defects in PCM

Abstract

Parasitic capacitance and resistance have much influence on the performance of the phase change memory (PCM). Based on SPICE circuit simulations, this paper investigates possible faults caused by the parasitic capacitance and resistance defects in stand-alone PCM cells. A realistic set of fault models are proposed and a test algorithm is proposed to test the faults.