Modeling and simulation of microcode Memory Built In Self Test architecture for embedded memories

Abstract

Memory Built-in Self Test (MBIST) or as some refer to it array built-in self-test is an amazing piece of logic. Without any direct connection to the outside world, a very complex embedded memory can be tested efficiently, easily and less costly. Modeling and simulation of Microcode MBIST is presented in this paper. The design architecture is written using Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using Xilinx ISE tools. The architecture is modeled and synthesized using register transfer level (RTL) abstraction. Verification of this architecture is carried out by testing stuck at fault SRAM. Five BIST algorithms are implemented i.e MATS, MATS+, MARCH X, MARCH C and March C-to test the faulty SRAM.