Modeling and Simulation of a Large Integrated Circuit Package

Abstract

The first full-wave signal integrity analysis of a complete computer chip package is presented. The simulations are based on the Finite Integration Technique in the time domain. The handling of the highly complex package geometry and of the huge amount of unknowns arising in the discretization is made possible by use of massive parallelization. The latter employs an optimally balanced partitioning technique. Simulation results including signal delay times and cross-talk couplings are given.