Modeling and Simulation Analysis of Junctionless Transistors with Double Gates

Abstract

A simple analytical model for the drain current and threshold voltage for junctionless transistors with double gates is presented. This model provides a relatively exact and continuous description of junctionless transistor behaviour in all operating regions. Besides, the influence of different structure parameters such as the channel length, silicon layer thickness, gate oxide thickness, and the doping density on the drain current and threshold voltage is discussed. The analytical model solutions are compared with the numerical results obtained by using the COMSOL Multiphysics simulator. In addition, the influences of the channel length on the sub-threshold swing, threshold voltage, and Drain Induced Barrier Lowing are investigated in the simulation model. Moreover, by adding interface traps to the gate in the model, the effects of interface traps on transferring characteristics and the threshold voltage of junctionless transistor are studied.