Modeling and bifurcation analysis of converters with power semiconductor filter

Abstract

An input filtering technique, named as “Power Semiconductor Filter (PSF)”, has been previously proposed. The idea is based on utilizing a series pass device (SPD) to profile the waveform of the input current of switched-mode power converters. Such solid-state filter can eliminate or reduce the use of bulky passive filters, so as to increase the power density of the entire converter. This paper will investigate into the bifurcation phenomena with the PSF using a peak-voltage modulator to regulate the voltage across the SPD. Detailed sampled-data modeling and stability analysis will be given. To tackle the occurrence of bifurcation, a compensation ramp introduced into the peak-voltage modulator will be proposed. The behaviors with and without the compensation ramp in the modulator will be demonstrated on a 48W, 40–140V/24V buck converter. By studying the eigenvalue locus on the z-plane, the models can predict the onset of limit cycles and illustrate how the compensation ramp can make the locations of the eigenvalues lie within unit cycle. Experimental results and theoretical predictions are in close agreement.