Abstract
Characteristics of transient latchup due to noise excitation through the gate of a parasitic SCR are measured and described by a new simplified model to clarify latchup immunity in a double-well CMOS with a nonepitaxial substrate. The model accounts for the effects of high-level carrier injection and base transit delays of the two parasitic transistors, and it can describe the observed latchup transient faithfully if the model parameters are given according to the predetermined procedure. The noise-pulse-width dependence of the latchup trigger current is obtained as a function of current gain, transit time, and transistor base-emitter shunt resistance to show the last one most sensitive to the trigger current. The optimum parameters with the double well are deduced from study to relate the model to structural parameters.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
