Abstract
Parallelism applies widely in high power modules to raise the current capacity. This paper models and analyzes a 1200V/600A silicon carbide (SiC) MOSFET power module with multichip in parallel. The equivalent circuits of both current commutation power loop and driver loop are derived. The parasitic parameters are extracted by ANSYS Q3D. The parasitic inductance in the power loop is analyzed considering the mutual influence. The unbalanced layout of the driver loop would cause different switching characteristics of the paralleled chips. Mathematical models are built to analyze current distribution in power loop and the relationship between gate resistor and driver loop inductance. The unbalanced current sharing during the transient can be mitigated by adjusting the gate resistor of each chip. The switching characteristics of the SiC MOSFET power module are measured in the double pulse tester. The experimental results validate the analysis of parasitic parameters.
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