Modeling and Analysis of a High Gain and Low Noise Figure 90 nm CMOS LNA Using Noise Cancellation Technique

Archana Archana,Manish Kumar,Aasheesh Shukla

doi:10.1109/sasm51857.2021.9841126

Modeling and Analysis of a High Gain and Low Noise Figure 90 nm CMOS LNA Using Noise Cancellation Technique

Archana Archana, Manish Kumar + Show 1 more

https://doi.org/10.1109/sasm51857.2021.9841126

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Publication Date: Aug 20, 2021

Affiliation: GLA University

#90nm Complementary Metal Oxide Semiconductor #Low-noise Amplifier + Show 8 more

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Abstract

This paper demonstrate the designing of inductorless low-noise amplifier (LNA) in 90nm CMOS (Complementary metal oxide semiconductor) technology. Two paths are introduced in this LNA, one is common source (CS) and the other is common gate (CG). Power gain is realized by CS path and input matching is achieved by CG path. The implementation of noise cancellation technique provides and enhancement in the Noise Figure (NF). Here S<inf>11</inf> is negative for the entire band and S<inf>21</inf> is positive for the entire band. S<inf>11</inf> varies from −8 to −13.8dB and S<inf>21</inf> varies from 4 to 10.5 dB in the frequency range of 0–2.5 GHz. At 2.5 GHz, the minimum NF value is 3 dB.

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