Abstract
In this article, we propose a new method for fault tree analysis, called model synthesis, which comes in addition to traditional assessment techniques. It consists in rewriting the fault tree under study, or the set of minimal cutsets extracted from this fault tree, so to make some relevant information emerge.Our implementation of model synthesis relies on encoding Boolean formulas by means of zero-suppressed Boolean expression diagrams. Rewriting heuristics are efficiently implemented by means of local operations on these diagrams. A key feature of zero-suppressed Boolean expression diagrams is that they make it possible to perform partial normalization of Boolean formulas, avoiding in this way the exponential blow-up of calculation resources most of the other methods suffer from.We show how to take advantage of the architecture of the systems under study to guide rewriting heuristics. We illustrate the principles of model synthesis and of its implementation by means of examples.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
