Model Design of Electrically Erasable EEPROM Memory Cell

Lei Zhao

doi:10.4236/jcc.2020.84006

Abstract

This article introduces an EEPROM memory cell model that is different from the equivalent capacitance model. This model uses high-frequency components in circuit design, including MOS transistors, zener diodes, resistors, capacitors, etc., and builds a model that can be used in most analog environments. The simulation of the transient process of write and read operations helps designers understand the working principle of EEPROM, and it can also be applied to the overall circuit design. According to the structure and working principle of the EEPROM cell device, a model of its equivalent circuit is established, and the read, write, and erase operations of the EEPROM cell are transiently simulated using this model. The simulation results verify the correctness of the model.

Highlights

Flash Memory is gradually becoming the mainstream of mobile information equipment with high requirements on size, power consumption and flexibility due to its sturdy and compact integrated structure, low power consumption, and fast reading and writing [1]
The gate is connected to the Word Line (WL) and its drain Bit Line (BL)
The effects of the control gate voltage and write time on the performance of the floating gate EEPROM device were analyzed through the simulation results, which provided a basis for the model parameter verification

Summary

Introduction

Flash Memory is gradually becoming the mainstream of mobile information equipment with high requirements on size, power consumption and flexibility due to its sturdy and compact integrated structure, low power consumption, and fast reading and writing [1]. In instruments and other embedded systems (such as smart flow meters), it is usually necessary to store some setting parameters, field data, and other information. These information requirements are not lost when the system is powered off, and the original settings can be restored time. Traditional multi-time programmable memory uses a standard CMOS process, known as pure logic NVM. According to the structure and working principle of the EEPROM cell device, a model of its equivalent circuit is established, and the read, write, and erase operations of the EEPROM cell are transiently simulated using this model. It’s very important for EEPROM, directly related to the success of its design

EEPROM Cell Structure

Design of the Storage Unit Model

Storage Model Parameter Setting

Conclusions and Discussion