Model checking of global power management strategies in software with temporal logic properties

Abstract

Complex and sophisticated power management strategies are a commonplace design policies today in order to manage the power consumption of complex low power digital integrated circuits. These global power management strategies are implemented in software/firmware and are used to orchestrate the switching between power states of multiple power domains in local power controllers which resides in hardware. In this paper, we propose a methodology of verifying such global power management softwares with safety linear temporal logic (LTL) properties using bounded model checking based verification approach. We present our results on several test cases of significant complexity to demonstrate the feasibility of the proposed framework.