Abstract

Rose-Hulman is competing in EcoCAR2, a three year competition where teams design, build, and test a hybridvehicle architecture. Teams are required to generate vehicle models that will be used throughout the life of the competition. The model is used to choose a hybrid architecture, design a robust control scheme, implement fault mitigation strategies, and optimize vehicle performance. Modelling techniques include Model-in-the- Loop, Software-in-the-Loop, and Hardware-in-the-Loop. This paper will discuss the techniques developed to build a model that can be actively used for the life of the three year competition and maintained across the MIL, SIL, and HIL modelling levels.

Highlights

  • Rose-Hulman Institute of Technology is one of 16 universities competing in EcoCAR2: Plugging in to the Future [1], a three year international competition where teams are challenged to design, build, and test a hybrid vehicle architecture utilizing alternative fuels to reduce the energy consumption and emissions production of a 2013 Chevrolet Malibu

  • Teams are required to generate vehicle models that will be used throughout the life of the competition

  • EVS26 International Battery, Hybrid and Fuel Cell Electric Vehicle Symposium the HVSC Logic block is compiled into C code, the same code that will be deployed on the target

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Summary

Introduction

Teams are presently in year one of the competition where students choose an architecture, specify components, and design the vehicle. Design includes both the mechanical integration of the parts as well as design of the supervisory control system for the hybrid system. The model is used to model stock vehicle performance, choose a hybrid architecture, and come up with a basic control scheme. Teams are required to use several modeling techniques including Model-in-the-Loop (MIL), Software-in-the-Loop (SIL), and Hardware-in-theLoop (HIL) [2, 3]. In all cases (MIL, SIL, and HIL), the logic for the HVSC Logic block and the signals are the same. A change in the HVSC Logic in one model is automatically changed for the other models as the blocks are logically identical

Development Model Flow
Model Concurrency
Subsystem Component Layering
Layer Interfacing Standards
Signal Documentation
Future Work
Conclusion
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