Model 3D MOS capacitor system using regular arrays of vertical Si nanowires

Abstract

A model system of three-dimensional (3D) Si nanowire (SiNW) Metal-Insulator-Semiconductor (MIS) capacitor arrays with vertical Si nanowires of diameter 430 nm and height 1.35 and 2.5 µm respectively has been fabricated and studied. The gate dielectric was a 6 nm thick thermally grown SiO 2 layer and the gate metal was Al. The SiNWs were formed by using photolithography with an I-line stepper and reactive ion etching. We studied the increase in capacitance density due to the 3D nanostructuring of the capacitor surface by the SiNW formation and found that it scales quite well with the geometrical increase of the capacitor surface area. The exact knowledge of the number of SiNWs on the surface, as well as their homogeneity in size, allowed the extraction of the single SiNW capacitance and intrinsic series resistance. Also, properties such as the density of interface states, the flat band voltage and the voltage at which the nanowire becomes fully depleted are determined.