Abstract
Strained thin-film transistors have been made by releasing the silicon layer of a silicon-on-insulator (SOI) wafer to realize better devices. Stretching a silicon thin film by a transfer process makes it easier for electrons to flow through the film and hence improves the performance of electronic devices. Jong-Hyun Ahn from Yonsei University and colleagues have realized a simple and cost-effective way for achieving this. After fabricating devices on a SOI wafer, they etched the handle silicon layer of a SOI wafer to leave a suspended silicon–silicon dioxide membrane. Residual oxidation-induced compressive strain in the buried oxide layer of the wafer created the desired strain and introduced it to the top silicon layer. This transfer-process-based approach reduced the number of defects in silicon and enabled devices to be transferred to plastic substrates to realize flexible devices.
Highlights
The volumetric expansion of SiO2 is constrained because it is bonded to the underlying Si handle wafer, and a high residual compressive stress of 0.2–6 GPa is biaxially developed in the buried oxide (BOX) layer.[22,23,24,25,26]
Etching out of the underlying handle Si leads to a biaxial expansion of the BOX and, as a result, creates biaxial tensile strain in the top Si ribbon that is tightly bonded to the BOX
Biaxial tensile strain was residually generated in the Si layer of a Si/SiO2 structure by utilizing the oxidation-induced volumetric strain of the BOX layer in SOI wafers
Summary
A critical path in the development of advanced silicon electronics involves a reduction in the dimensions of device geometries such as the channel thickness, channel length and gate dielectric thickness to increase the operating speed with lower power consumption and the density of integration in circuits.[1,2,3,4] Continued performance improvement through geometric scaling has faced increasingly difficult challenges.[5,6] Recent research focused on this issue has explored strain engineering that can increase the charge carrier mobility by creating tensile strain in Si with a capping stressor film,[7] local stressors under channel[8] or embedded source/drain stressors.[9,10] In particular, the introduction of an Si1 − xGex buffer layer with a large lattice constant represented by an epitaxial template can successfully generate biaxial tensile strain in Si.[11,12] The Si1 − xGex virtual buffer layer allows the fabrication of wafer-scale strained Si membranes[13,14] and approximate doubling of the mobility enhancement factors of electrons in Si layers for fast, flexible electronic device applications.[15,16,17] the process for introducing the Si1 − xGex buffer leads to undesirable misfit dislocations and interdiffusion of Ge in the Si/SiGe interface and requires uniform growth of the Si1 − xGex layer with precisely controlled composition of Si and Ge, which is challenging.[18,19,20,21]
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