Abstract
The new ESD surge simulation method that combines 3D pseudo-lchip device model consisting of internal LDMOS cell & peripheral LDMOS cell and hydrodynamic physical model is proposed in order to analyze the ESD destruction mechanism of LDMOS and optimize the cell layout against ESD for the first time. The simulation results show good agreement with experiments on ESD endurance and surge current crowding phenomena at peripheral cell causing poor ESD endurance. Utilizing the proposed simulation method, we developed new LDMOS cell layout achieving super high ESD endurance over 25kV/mm2.
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