Abstract
The PFC Boost Converter is an integral part of modern power supplies to improve power factor in electronic devices. The inherent problem associated with it is common mode (CM) Electromagnetic interference (EMI) noise arising due to the higher switching transition rate (dv/dt). The main coupling path for the CM noise is provided by parasitic capacitance occurring between the switching node and ground. In this scenario, it is important to identify feasible solutions for CM noise reduction. This paper therefore develops a circuit model for a boost PFC converter allowing detailed analyses of the performance of this type of converter. It includes all parasitic components along the CM noise path. Using this CM noise model, a novel balancing approach is proposed that mitigates CM noise in a PFC boost converter. Validation of the new design approach is supported by experimental results demonstrating substantial noise reduction for a balanced PFC boost converter.
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