Mitigation Effects of Decoupling Cells on Full Adders Process Variability

Abstract

To mitigate variability effects, this work explores decoupling cells on different adder topologies using a 7nm FinFET technology. Process variability shows an impact of up to 20% on nominal voltage and superior to 50% at near-threshold operation. After the insertion of DCells on the evaluated full adders, the circuits operating at nominal voltage present an increase of up to 20% on the robustness to delay variability and 40% on power consumption variability, with less than 20% of penalty in power and delay. Moreover, this technique adoption has a high impact on the results of circuits operating at near-threshold voltage; in some cases, reaching more than 40% reduction in performance for a small reduction in variability.