Abstract
Low power design techniques like clock gating incur side-effect of increasing current variation drawn by processors.Current variation produces voltage ripples due to parasitic inductance in power supply networks.Voltage emergency occurs when voltage drops below threshold,which may result in system malfunction because of timing faults.This work characterized the relationship between voltage emergencies and memory access behaviors in simultaneous multithreading processors.And then proposed a thread scheduling strategy utilizing memory level parallelism to mitigate voltage emergencies.Experimental results show that,compared with existing work,the proposed strategy reduces voltage emergencies by 21.7% and 25.2% for 2-thread workloads and 4-thread workloads respectively,and achieves better overall balance between performance and fairness.
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