Mitigating shift-based covert-channel attacks in racetrack last level caches

Abstract

Racetrack memory (RM, also known as DWM (domain wall memory)) is an emerging memory technology that has many advantages such as low power, high density, and low access latency. Recent studies have shown that it is promising to architect RM as last level cache (LLC). Given that a RM track consists of m domains (for storing m bits data) and n access heads (1≤n<m), one RM access often requires multiple hops of shift to move the access head above the domain to be accessed. This leads to variant access latency, which may be exploited to initiate covert channel attacks to leak sensitive information in secure computing environment. In this paper, we elaborate the feasibility of such attacks and propose secure head management policies to effectively mitigate the attacks in RM LLCs. Our experimental results show that the proposed schemes can reduce the new discovered shift-based covert channel's capacity by up to 260 times with modest performance overhead.