Mirror image: newfangled cell-level layout technique for single-event transient mitigation

Abstract

Recent years, the hardening of combinational circuits is becoming a common concern. Unlike the transistor-level hardening technique, the cell-level hardening technique, a divide and conquer strategy, can substantially make use of some typical character in the cell-circuit module to mitigate single event transient (SET) sensitivity. The mirror image (MI) technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure. 3D TCAD mixed-mode simulation have been performed in 65 nm twin-well bulk CMOS process, the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25 %, and can mitigate the SET pulse width from the posterior-stage PMOS about 10 %. The MI technique, a represent of the cell-level technique, may be the future of the hardening of combinational circuits.