Minimizing Voiding in Bottom Terminated Components by Optimizing the Solder Paste Flux

Abstract

Abstract Perhaps the single biggest challenge in PCB assembly today is voiding under bottom terminated components (BTCs) such as QFNs (quad-flat-pack, no-leads), D-Paks, and LGAs (land grid arrays). Many bottom terminated components, such as QFNs, have a large thermal pad on the bottom side which provides excellent thermal and electrical grounding properties. However, effectively soldering these components to minimize thermal pad voiding can be a challenge. Many automotive electronics assemblers are increasing this challenge by requiring less than 10% voids to improve reliability. The large deposit of printed solder paste required to solder the thermal pad typically induces flux entrapment and subsequent voiding during the reflow process. Large voids and/or a high number of voids cause decreased thermal conductivity and lower the mechanical strength of the resulting solder joints. The large solder paste deposit required may also cause the component to float and open up the electrical connections around the perimeter of the component. Another factor affecting voiding has been the transition to lead-free solder, which has been marked by the use of various SAC alloys. Most applications for surface mount assembly use SAC305 (96.5Sn/3.0Ag/0.5Cu) with a melting temperature range of 217–220°C. The higher temperatures required for lead-free soldering and the increased surface tension of the SAC alloy exacerbate the voiding issue. This paper will focus on the techniques for optimizing the assembly process for QFN components, with a focus on minimizing voiding. Best practices for lead-free reflow profiling, stencil aperture design, solder paste volume control, and the importance of flux chemistry to minimize void formation will be discussed.