Abstract
This paper proposes techniques for floorplanning in 3-D ICs. Although floorplanning has been extensively studied for last few decades. But increase in the scale of floorplanning instances, new architectures and ever evolving algorithms provides the motivation to incorporate new improved techniques to provide optimal solution. 3D ICs are better in performance compared to their 2-D representation because they occupy smaller die area, consume less power, have smaller wirelength and are lower in cost and hence perform better. In this paper we have proposed a heuristic based algorithm to reduce the Through Silicon Vias(TSVs) and Satisfiability Modulo Theories(SMT) driven floorplanning of the tiers. Our proposed work is successful in reducing the number of vias required in most of the GSRC and MCNC benchmarks benchmarks considerably. The proposed technique has given a good solution in terms of reduction in wirelength also.
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