Minimizing power supply noise through harmonic mappings in networks-on-chip

Abstract

Power supply integrity has become a critical concern with the rapid shrinking of device dimensions and the ever increasing power consumption in nano-scale integration. Particularly, power supply noise is strongly correlated to the spatial distribution of activity densities and this can be attributed to the on-chip communication, which dictates the power dissipation and overall system performance in networks-on-chip. In this paper, we propose a new mapping strategy aiming to create a balanced activity distribution across the whole chip. We formulate the problem of application mapping as a minimization of the activity density by employing a repulsive force-based objective function. Metrics of regional activity density and characteristics of its impact on power supply noise are considered. The proposed method has been rigorously evaluated based on a large set of real-application benchmarks. Significant reduction in power supply noise can be achieved with negligible energy overhead. This new approach would provide a more scalable solution for future large-scale system integration.