Abstract
Most modern digital receivers sample the received RF signal at an intermediate frequency (IF), then downconvert to the baseband in the digital domain. The baseband samples are subsequently correlated with a time-limited square pulse, which is readily implemented as an integrator. Since correlation is performed at the sampling frequency, the receiver correlates at an unnecessarily high frequency. This high frequency results in significant power dissipation especially if parallel correlators are employed. By downsampling after appropriate filtering to slightly above the signal Nyquist rate, correlation is achieved at a fraction of the sampling frequency, resulting in corresponding reduction in power consumption. Furthermore, by resampling to an integer number of samples per chip, architectural changes in the correlators are possible, allowing even more reduction in power consumption. In this paper, a resampling correlator with minimal hardware overhead that outperforms the conventional correlator is presented.
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More From: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
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