Minimizing linewidth roughness in Step and Flash Imprint Lithography

Abstract

Optical lithography has been successful in achieving deep sub-wavelength images by the continuous improvement of lens systems, resists and the introduction of phase shift masks. One of the key challenges in attempting to pattern feature sizes less than 32nm is the ability to minimize feature roughness while maintaining acceptable process throughput. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Step and Flash Imprint Lithography is a step-and-repeat imprint process that has demonstrated excellent feature resolution. Since the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. In this paper, LWR was evaluated for several different templates. Feature sizes ranging from 20nm to 50nm were studied, and LWR was calculated from SEM images of the template, on imprinted wafers, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size. A minimum LWR of 1.7nm was achieved, which is the required LWR for processing at the 32nm node.