Abstract
Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guard bands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guard band and performance loss from lowering the voltage.
Highlights
Fin Field-Effect Transistor (FinFET) devices are widely used, due to their reduced leakage and excellent subthreshold slope compared to planar MOSFET
We explain how multi-core systems are affected by Self Heating Effect (SHE) and N-Zero-Temperature Coefficient (ZTC) in terms of performance, power, and energy
We presented our algorithm aiming to accurately locate the proper voltage to operate at VZTC
Summary
Fin Field-Effect Transistor (FinFET) devices are widely used, due to their reduced leakage and excellent subthreshold slope compared to planar MOSFET. Self Heating Effect (SHE) refers to elevated channel temperatures (TC ) and their impact on the performance of the transistor. Reference [6] shows ITD impact on performance in a 65nm CMOS ring oscillator simulations using SPICE in the sub-threshold regime This quantitative study shows that ZTC occurs at VZTC = 0.9V. SELF HEATING MODELING To study the impact of SHE on large circuits, we enhance and employ the standard EDA tools. Modeling Self-Heating Effects: In this work, we employ the model typically used in SPICE circuit simulations It relies on a RC-thermal network to model SHE. Such a high TC occurs under worst-case corner (continuous heating due to DC currents, high fin counts, high voltage).
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