Minimize the delay of parasitic capacitance and modeling in RLC circuit

Abstract

This paper shows that how to minimize the delay. We changed several elements to minimize the delay in the circuit. Simulation results show the best effect when the value of parasitic capacitance is changed. We found eligible point by simulating Parasitic Capacitance case by case based and proved it. Types of case are Elmore delay, Interconnection delay, lowering ParasiticCapacitance's parameter entirely, raising Parasitic Capacitance's parameter in order of precedence, lowering Parasitic Capacitance's parameter in order of precedence, and changing inverter's W parameter. And it has been apparently proven that case of using parasitic capacitance is better than other methods.