Minimization of the muGFET contact resistance by integration of nisi contacts on epitaxially raised source/drain regions

Abstract

High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we endeavor to integrate a low temperature selective epitaxial growth process and a low temperature NiSi process to form low resistance S/D contacts. Our experimental results show 34% and 11% improvement in parasitic S/D resistance of N-and P-channel multiple gate FETs with less than 20 nm wide fins respectively.