Abstract
A conventional Network-on-Chip (NoC) router uses input buffers to store in-flight packets. These buffers improve performance, but consume significant power. It is possible to bypass these buffers when they are empty, reducing dynamic power, but static buffer power, and dynamic power when buffers are utilized, remain. To improve energy efficiency, buffer less deflection routing removes input buffers, and instead uses deflection (misrouting) to resolve contention. However, at high network load, deflections cause unnecessary network hops, wasting power and reducing performance. In this work, we propose a new NoC router design called the minimally-buffered deflection (MinBD) router. This router combines deflection routing with a small "side buffer," which is much smaller than conventional input buffers. A MinBD router places some network traffic that would have otherwise been deflected in this side buffer, reducing deflections significantly. The router buffers only a fraction of traffic, thus making more efficient use of buffer space than a router that holds every flit in its input buffers. We evaluate MinBD against input-buffered routers of various sizes that implement buffer bypassing, a buffer less router, and a hybrid design, and show that MinBD is more energy efficient than all prior designs, and has performance that approaches the conventional input-buffered router with area and power close to the buffer less router.
Highlights
A network-on-chip is a first-order component of current and future multicore and manycore CMPs (Chip Multiprocessors) [10], and its design can be critical for system performance
We propose minimally-buffered deflection routing (MinBD) as a new NoC router design that combines both bufferless and buffered paradigms in a more fine-grained and efficient way
As we show in our evaluations, MinBD provides higher energy efficiency while providing high performance, compared to a comprehensive set of baseline router designs
Summary
A network-on-chip is a first-order component of current and future multicore and manycore CMPs (Chip Multiprocessors) [10], and its design can be critical for system performance. AFC requires the control logic for both forms of routing to be present at each network node, and requires power gating to turn off the input buffers and associated logic at low load Another prior design, the Chaos router [23], combines buffering with deflection, but still uses its input buffers for every flit that arrives. The router performs deflection routing, but can choose to buffer up to one flit per cycle in a small side buffer, which significantly reduces deflection rate and enhances performance compared to a pure bufferless design while requiring smaller buffer space than a conventional input-buffered design.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have