Abstract
This paper presents a new approach for estimating power dissipation in a high performance microprocessor chip. A characteristic profile (including parameters such as the cache miss rate, branch-prediction miss rate, pipeline stalls, instruction mix, and so on) is first extracted from the application programs. Mixed-integer linear-programming and heuristic rules are then used to gradually transform a generic program template into a fully functional program. The synthesized program exhibits the same characteristics (and hence the same performance and power-dissipation behavior), yet it has an instruction trace that is orders of magnitude smaller than the initial trace. The synthesized program is subsequently simulated on a register-transfer-level description of the target microprocessor to provide the power-dissipation value. Results obtained for Intel's Pentium processor executing standard benchmark programs show a simulation-time reduction of three to five orders of magnitude.
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