Microprocessor power delivery challenges in the Nano-Era

Abstract

A robust power grid is pivotal in meeting performance targets and guaranteeing reliable operation of high-performance microprocessors. Higher device densities and faster switching frequencies cause large switching currents through flow through the power and ground networks which degrade performance and reliability. Excessive resulting voltage drops in the power grid reduce switching speeds and decrease noise margins of the circuits and inject noise which may lead to functional failures. Further, high average current densities lead to undesirable wearing out of metal wires due to electro-migration. Achieving and maintaining excellent voltage regulation at the consumption points notwithstanding the wide fluctuations in the power demands across the chip is definitely the key to avoiding an unruly power grid. During this tutorial, I plan on talking about not only the fundamentals of on-die power delivery but also discusses chief challenges involved in designing a robust and reliable power grid including verification against design targets using in-house/vendor tools in the nano-era.