Abstract
In this paper, a voltage source inverter (VSI) with a finite error convergence time controller is presented. A Sliding Mode Control (SMC) has used in many applications due to their robustness, but the convergence of the system states to the equilibrium point is normally asymptotic in infinite time. Recently, terminal sliding mode control (TSMC) not only guarantees the finite error convergence to the manifold from any initial states and the finite error convergence reaching time to the equilibrium point but also reserved the merits of the SMC. With this proposed TSMC parameters design, the inverter output voltage will track the sinusoidal reference voltage within very short time. Thus, the performance of the inverter can be improved. Experimental results are given to verify the theoretical analysis. For comparison purposes, a classic sliding mode controlled VSI is also tested on the same experimental system.
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