Micro-APP: a building block for low-cost high-speed associative parallel processing

Abstract

A design technique, which allows the data-storage and the word-control functions of a byte-organized variable record-length Associative Parallel Processor (APP), to be integrated on a single l.s.i. chip is discussed, and a new l.s.i. device, called the Micro-APP, is proposed. Two implementations of the Micro-APP (16 words × 16 bits and 32 words × 12 bits) are described and their characteristics compared with a similar APP in which all functions are implemented separately. Improvements of 16% and 112% in bit-per-pin ratio and reductions of 96% and 94% in cost-per-word-row are reported. Minimum times for a search/write cycle (with tag resolution) of 190ns and 220ns are also recorded.