Metrology technology for the 70-nm node: process control through amplification and averaging microscopic changes

Abstract

Below the 70-nm node feature sizes and aspect ratios will require great advances in metrology and defect detection capability. Although the International Technology Roadmap for Semiconductors (ITRS) prediction becomes more aggressive with each revision, isolate gate lengths for the 70-nm node are predicted to be below 40 nm for microprocessors (see 2000 ITRS). 70 nm and below feature sizes and high aspect ratios will be characteristic of on-chip interconnect. Memory devices will achieve line densities that will drive all areas of metrology. The device performance required for increasing clock speed and reducing leakage current has been driving new gate stack materials development which is expected to be ready for manufacture at this node and below. On-chip interconnect will have integrated low /spl kappa/ dielectric, copper metal lines, and copper diffusion barrier layer materials predicted by the roadmap will require interconnect design advancements to meet increased clock speeds even if the present rate of advance in clock speed decreases. In this paper, the key metrology and defect detection trends for wafer manufacture are covered. The best available information on critical dimension, gate stack, and interconnect measurement and data management are described in light of the need to obtain statistically relevant information from microscopic features.