Abstract
Approximate computing has emerged as an efficient solution for energy saving at the expense of calculation accuracy, especially for floating-point operation intensive applications, which have urgent demands for some uniform design frameworks for floating-point approximate computing combining the approximate computing techniques with the metrics of applications. In this paper, a simple approximate method with a zero-mean noise for the mantissa was introduced firstly, called PAM. Secondly, based on the proposed approximate method, the corresponding noise propagation models for floating-point operations were built, including floating-point addition, subtraction, and multiplication. Thirdly, a uniform design framework, which is only related to the operational-level topology of applications, was presented. The presented design framework can be used to evaluate the quality of data produced by applications before the circuit design is completed, and the efficient bit width of the mantissa can be obtained under specific requirements, which is also suitable for truncation. Finally, we studied the feasibility of the proposed design framework through two typical applications of image processing, edge detection and Gaussian filtering. The experimental results of edge detection have shown that our proposed design framework could effectively predict efficient bit width under the specific peak signal-to-noise ratio, with a difference of 1–2 bits in extreme situations. The Gaussian filtering experiment has demonstrated that the proposed design framework could apply to applications with complex calculations and structures.
Highlights
With the ever-increasing quest for performance and high integration, power consumption has become a crucial issue
We assumed that the input operands are in floating-point number format, which consists of three parts: the sign bit, the exponent bits and the mantissa bits
We introduced a noise distribution with zero-mean into the method, through which noise propagation models for multiplier, adder, and subtracter were established
Summary
With the ever-increasing quest for performance and high integration, power consumption has become a crucial issue. Some approximate approaches for FP adders and FP multipliers were proposed [16]- [19], it still lacks some design frameworks for FP AC to guide our design and help us to estimate the quality of data during the design phase, especially those uniform design frameworks that can combine the AC techniques with the metrics of applications Such a framework is crucial for designers in project planning, and the framework that can be applied to truncation is more critical. Yan et al [24] proposed a configurable floatingpoint multiplier based on the K-nearest neighbor algorithm, called kNN-CAM, which lost 4.86% accuracy in exchange for 66.875% area-saving and 19.134% acceleration Their method was carried out based on truncation, which could predict the efficient bit width needed by the new data to reduce the consumption and area at the largest range.
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
