Methodology to Predict Substrate Warpage and Different Techniques to Achieve Substrate Warpage Targets

Abstract

With the continued demand for fine features, enhanced assembly yield, and improved reliability in the microelectronic packaging industry, there is a need to reduce substrate warpage. Factors such as coefficient of thermal expansion mismatch among several materials in the packaging substrate, modulus of different materials, thickness of different layers, orientation of features in each layer, thermal and mechanical loading conditions influence the substrate warpage, and any effort to reduce substrate warpage needs to address one or more of these factors. One technique to reduce warpage will be through the viscoelastic relaxation of the dielectric material, when other factors cannot be changed for performance, processing, or cost reasons. Thus, it is important to accurately model the viscoelastic relaxation of the dielectric material, and study how the warpage can be reduced either by changing dwell times at different temperatures and/or by introducing appropriate mechanical loads in combination with thermal loads. In this paper, we present two approaches to reduce substrate warpage: 1) by modifying the temperature-time profile of the sequential processing steps, and 2) by using an external mold to reduce the substrate warpage. Based on the simulation results, it appears that significant warpage reduction is achievable through the proposed techniques.