Methodology for Determination of Process Induced BTI Variability in MG/HK CMOS Technologies Using a Novel Matrix Test Structure

Abstract

Process variations in addition to random stochastic variations contribute to variability in aggressively scaled CMOS devices. To decouple the process variation from the random stochastic variations, a novel transistor test structure utilizing a matrix configuration is introduced. Based on this structure, it is shown that the local VT and local bias temperature instability (BTI)-induced variance scales inversely with the gate oxide area over a range of 1000x, whereas process variations lead to saturation in the variance when determined using samples across the wafer. The gate area dependence of the VT and the BTI-induced variance can be modeled independently using two stochastic processes.