Methodology for achieving best trade-off of area and fault masking coverage in ATMR

Abstract

The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults. However, it presents a minimum area overhead of 200% compared to the original circuit. In order to reduce area overhead without compromising significantly the fault coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized in area compared to the original module. Initial studies of this technique have shown that it is possible to reach a good balance between fault coverage and area overhead cost. In this work, we do a further analysis of this approach by using a new method to compute approximate functions and to select the best combinations of approximate circuits targeting the highest fault coverage. We use complex gates and employ structural reorder techniques. All the tests are done using a fault injection tool designed specifically for approximate TMR scheme. Results show that area overhead can be reduced greatly from 200% to 120%and still reaching fault coverage of more than 95%.