Method and utility for minimizing bitsliced representations of 4×4 S-boxes

Abstract

The article is devoted to methods and tools for generating bitsliced descriptions of bijective 4×4 S-Boxes with a reduced number of gates/instructions. Bitsliced descriptions generated by the proposed method make it possible to improve the security and performance of both software implementations of cryptoalgorithms using 4×4 S-Boxes on various processor architectures, as well as FPGA and ASIC based hardware. The paper develops a heuristic method of minimization that uses standard logical instructions AND, OR, XOR, NOT, which are available in most 8/16/32/64-bit processors. Due to the combination of different heuristic techniques (preliminary calculations, exhaustive search to a certain depth, DFS algorithm, refining search) in the method, it was possible to reduce the number of gates in bitsliced descriptions of S-Boxes compared to other known methods. The corresponding software in the form of a utility in the Python language was developed and its operation was tested on 225 S-Boxes of various cryptoalgorithms. It is found that the developed method generates a bitsliced description with a smaller number of gates in 57 % of cases compared to the best known methods implemented in the LIGHTER/Peigen utilities.