Metastability behavior of CMOS ASIC flip-flops in theory and test

Abstract

Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>