Abstract

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship Ids–Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage Ctot–Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

Highlights

  • Graphene has recently attracted a lot of attention

  • Popular metal-oxide-graphene field-effect transistor (MOGFET) models do not take into account the detrimental effect of Dit states on device surface potential [4,5]

  • Zebrev et al [6], recently presented a model that takes into account the effect of Dit states on the device current

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Summary

Introduction

Graphene has recently attracted a lot of attention. Its 2D nature along with its significantly high carrier mobility (≈15,000 cm2/(V·s)) make it an ideal material to replace silicon [1] in the more than Moore era. The extracted Cit is referred to as Cit_exp as device’s interface trap capacitance obtained from experimental Ctot–Vgs data.

Results
Conclusion

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