Metal-nitride-oxide-silicon field-effect transistors, with self-aligned gates

Abstract

Silicon insulated-gate field-effect transistors (FETs) have been fabricated by processes involving relatively non-critical photoresist and self-limiting etching steps. Important features of the method include the formation of the gate insulator under extremely clean conditions, incorporation of an alkali ion barrier (silicon nitride) to achieve stable device characteristics and automatic alignment of the gate electrode with respect to source and drain. The gate insulator, comprising 600 Å of grown silicon dioxide covered with 400 Å of silicon nitride, is formed at the beginning of fabrication. Thus, the SiSiO 2 interface is established at a point where the best state-of-the-art cleaning techniques can be applied to the starting material. A thick (8000 Å) layer of SiO 2 is pyrolytically deposited over the nitride to minimize contact capacitances in the finished structure. This must be removed from the active device region, and advantage is taken of the difference in etch rate between SiO 2 and silicon nitride to ensure a well-controlled gate insulator thickness. Thus the nitride layer serves the dual function of providing a barrier to mobile ions in the completed structure, and of acting as an etch-resistant layer during fabrication to achieve control over geometry. A polycrystalline layer of silicon is used to form the gate electrode, which is shaped early in the process, and is used to define the limits of the source and drain windows. This aspect of the fabrication assures self-alignment of the gate electrode with respect to source and drain. During the diffusion of source and drain regions the polycrystalline silicon is rendered sufficiently conductive that no metallization of the gate electrode is required, except at one end for contacting purposes. This eliminates the need for a critical photoresist alignment. Both n and p induced-channel (enhancement) devices have been made with this process. Turn-on voltages at 10 μA drain current of +1.35 V ( n-channel) and −2.6 V ( p-channel) with less than 12 per cent spread over a slice were obtained. Analysis of the device characteristics indicates field-effect mobilities of 335 and 233 cm 2/V-sec for the n- and p-channel devices respectively. Aging behavior under bias at 300°C indicates the presence of residual mobile positive charge of the order of 1.5 × 10 11 charges/cm 2, resulting in turn-on voltage shifts of less than 1 V over several hundred hr with +10 V applied to the gate.