Abstract
A distinctly new route for the design, modeling and electrical behavior of very short-channel (5–10 nm in channel length) nanowire field-effect transistors (FETs) has been presented. Essential elements of the approach entail a drain current determined by thermionic emission, but not by carrier mobility in the channel of the transistor. A basic understanding of the fundamental physics and the concepts of Schottky-barrier-based design for the proposed route have been described. Quantum confinement in the nanowire channel together with Schottky barrier tailing and temperature-dependent fluctuations of applied biases has been taken into account for the development of the model. Both current–voltage characteristics and transconductance of FETs have been studied. The calculated results are in near-quantitative agreement with the available experiments. Measured data show very diverse (e.g., exponential, linear, saturating, and non-linear non-exponential non-saturating) nanowire transistor characteristics. The model explains these characteristics well and reveals a number of new transistor actions. It highlights the impacts of quantum confinement and Schottky contacts for these new transistor actions. It also quantifies the significant enhancement of the drain–source current and transconductance. With new findings thus achieved, suggestions for the realization of very high-performance, small-diameter (preferably 2 nm), small-Schottky-barrier-height, high-operating temperature, ultra-short-channel-length, nanowire transistors have been made. Optimized design of these transistors has been suggested. And the range (in terms of device and technological parameters) of the proposed model has been elucidated.
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